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MRF89XA
2.7
Interrupt (IRQ0 and IRQ1) Pins
2.9
Transmitter
The Interrupt Requests (IRQ0 and IRQ1) pins 21 and
22, provide an interrupt signal to the host
microcontroller from the MRF89XA. Interrupt requests
are generated for the host microcontroller by pulling the
IRQ0 (pin 21) or IRQ1 (pin 22) pins low or high based
on the events and configuration settings of these
interrupts. Interrupts must be enabled and unmasked
before the IRQ pins are active. For detailed functional
description of interrupts, see Section 3.8, Data
Processing .
2.8 DATA Pin
After OOK or FSK demodulation, the baseband signal
is available to the user on the DATA pin (pin 20), when
Continuous mode is selected. Therefore, in Continuous
mode, the NRZ data to or from the modulator or
demodulator respectively is directly accessed by the
host microcontroller on the bidirectional DATA pin. The
SPI Data, FIFO and packet handler are therefore
inactive. In Buffered and Packet modes, the data is
retrieved from the FIFO through the SPI.
During transmission, the DATA pin is configured as
DATA (Data Out) and with internal Transmit mode
disabled; this manually modulates the data from the
external host microcontroller. If the Transmit mode is
enabled, this pin can be tied “high” or can be left
unconnected.
During reception, the DATA pin is configured as DATA
(Data In); this pin receives the data in conjunction with
DCLK. DATA pin (unused in packed mode) should be
pulled-up to VDD through a 100 k ? resistor.
The transmitter chain is based on the same double-
conversion architecture and uses the same
intermediate frequencies as the receiver chain. The
main blocks include:
A digital waveform generator that provides the I and Q
base-band signals. This block includes digital-to-
analog converters and anti-aliasing low-pass filters.
A compound image-rejection mixer to up-convert the
baseband signal to the first IF at one-ninth of the carrier
frequency (f rf ), and a second image-rejection mixer to
up-convert the IF signal to the RF frequency transmitter
driver and power amplifier stages to drive the antenna
port.
FIGURE 2-6:
TRANSMITTER ARCHITECTURE BLOCK DIAGRAM
Amplification
Second
up-conversion
First
up-conversion
I
Q
Interpolation
filters
LO2 TX
DACs
DDS
Waveform
Generator
Data
Clock
I
RFIO
PA
Q
LO1 TX
I
Q
LO2 TX
RF
? 2010–2011 Microchip Technology Inc.
IF
Preliminary
Baseband
DS70622C-page 19
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